View W78LE812F-24_122783.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

W78LE812 8-BIT MTP MICROCONTROLLER
GENERAL DESCRIPTION
The W78LE812 is an 8-bit microcontroller which can accommodate a wide range of supply voltages with low power consumption. The instruction set for the W78LE812 is fully compatible with the standard 8051. The W78LE812 contains an 8K bytes MTP ROM (Multiple-Time Programmable ROM); a 256 bytes RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 6-bit I/O port P4; three 16-bit timer/counters; a hardware watchdog timer and a serial port. These peripherals are supported by a fourteen sources two-level interrupt capability. To facilitate programming and verification, the MTP-ROM inside the W78LE812 allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security. The W78LE812 microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor.
FEATURES
* Fully static design 8-bit CMOS microcontroller * Wide supply voltage of 2.4V to 5.5V * 256 bytes of on-chip scratchpad RAM * 8 KB electrically erasable/programmable MTP-ROM * 64 KB program memory address space * 64 KB data memory address space * Four 8-bit bi-directional ports * Three 16-bit timer/counters * Timer 2 Clock-out * One full duplex serial port(UART) * Watchdog Timer * Direct LED drive outputs * Fourteen sources, two-level interrupt capability * Wake-up via external interrupts at Port 1 * EMI reduction mode * Built-in power management * Code protection mechanism * Packages:
- DIP 40: W78LE812-24 - PLCC 44: W78LE812P-24 - PQFP 44: W78LE812F-24
-1-
Publication Release Date: February 1999 Revision A2
W78LE812
PIN CONFIGURATIONS
40-Pin DIP (W78LE812)
INT2,,T2, P1.0 INT3,T2EX, P1.1 INT4,P1.2 INT5,P1.3 INT6,P1.4 INT7,P1.5 INT8,P1.6 INT9,P1.7 RST A9CTRL,RXD, P3.0 A13CTR,LTXD, P3.1 A14CTRL,INT0, P3.2 OECTRL,INT1, P3.3 T0, P3.4 T1, P3.5 CE,WR, P3.6 OE,RD, P3.7 XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD P0.0, AD0 P0.1, AD1 P0.2, AD2 P0.3, AD3 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA,VPP ALE,P4.5 PSEN,P4.6 P2.7, A15 P2.6, A14 P2.5, A13 P2.4, A12 P2.3, A11 P2.2, A10 P2.1, A9 P2.0, A8
44-Pin PLCC (W78LE812P)
I N T 3 , T 2 E X , P 1 . 1 I N T 2 , T 2 , P 1 . 0
44-Pin PQFP (W78LE812F)
I N T 3 , T 2 E X , P 1 . 1 I N T 2 , T 2 , P 1 . 0
I N T 6 , P 1 . 4
I N T 5 , P 1 . 3
I N T 4 , P 1 . 2
P 4V .D 2D
A D 0 , P 0 . 0
A D 1 , P 0 . 1
A D 2 , P 0 . 2
A D 3 , P 0 . 3
I N T 6 , P 1 . 4
I N T 5 , P 1 . 3
I N T 4 , P 1 . 2
P 4V .D 2D
A D 0 , P 0 . 0
A D 1 , P 0 . 1
A D 2 , P 0 . 2
A D 3 , P 0 . 3
INT7,P1.5 INT8,P1.6 INT9,P1.7 RST A9CTRL,RXD, P3.0 P4.3 A13CTRL,TXD, P3.1 A14CTRL,INT0, P3.2 OECTRL,INT1, P3.3 T0, P3.4 T1, P3.5
6 5 4 3 2 1 44 43 42 41 40 7 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 29 17 18 19 20 21 22 23 24 25 26 27 28 P 3 . 6 , / W R , / C E P 3 . 7 , / R D , / O E X T A L 2 XVPP TS42 AS. . L 00 , 1 A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2
P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA,VPP P4.1 ALE,P4.5 PSEN,P4.6 P2.7, A15 P2.6, A14 P2.5, A13
INT7,P1.5 INT8,P1.6 INT9,P1.7 RST A9CTRL,RXD, P3.0 P4.3 A13CTRL,TXD, P3.1 A14CTRL,INT0, P3.2 OECTRL,INT1, P3.3 T0, P3.4 T1, P3.5
1 2
44 43 42 41 40 39 38 37 36 35 34 33 32 31 3 30 4 29 5 28 6 27 7 8 26 9 25 10 24 23 11 12 13 14 15 16 17 18 19 20 21 22 P 3 . 6 , / W R , / C E P 3 . 7 , / R D , / O E X T A L 2 XVPPP TS422 AS.. . L 001 ,, 1 AA 89 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2
P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA,VPP P4.1 ALE,P4.5 PSEN,P4.6 P2.7, A15 P2.6, A14 P2.5, A13
-2-
W78LE812
PIN DESCRIPTION
SYMBOL
EA
PSEN
ALE RST XTAL1 XTAL2 VSS VDD P0.0-P0.7
P1.0-P1.7
P2.0-P2.7 P3.0-P3.7
DESCRIPTIONS EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of external ROM. It should be kept high to access internal ROM. The ROM address and data will not be present on the bus if EA pin is high and the program counter is within on-chip ROM area. Otherwise they will be present on the bus. PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the Port 0 address/data bus during fetch and MOVC operations. When internal ROM access is performed, no PSEN strobe signal outputs from this pin. This pin also serves the alternative function P4.6. ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates the address from the data on Port 0. This pin also serves the alternative function P4.5 RESET: A high on this pin for two machine cycles while the oscillator is running resets the device. CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external clock. CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1. GROUND: Ground potential POWER SUPPLY: Supply voltage for operation. PORT 0: Port 0 is a bi-directional I/O port which also provides a multiplexed low order address/data bus during accesses to external memory. The pins of Port 0 can be individually configured to open-drain or standard port with internal pull-ups. PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate functions which are described below: T2(P1.0): Timer/Counter 2 external count input T2EX(P1.1): Timer/Counter 2 Reload/Capture control INT2-INT9 (P1.0-P1.7):External interrupt 2 to 9 PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory. PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. The pins P3.4 to P3.7 can be configured with high sink current which can drive LED displays directly. All bits have alternate functions, which are described below: RXD(P3.0) : Serial Port receiver input TXD(P3.1) : Serial Port transmitter output INT0 (P3.2) : External Interrupt 0
INT1(P3.3) : External Interrupt 1 T0(P3.4) : Timer 0 External Input T1(P3.5) : Timer 1 External Input WR (P3.6) :External Data Memory Write Strobe RD (P3.7) : External Data Memory Read Strobe PORT 4: A 6-bit bi-directional I/O port which is bit-addressable. Pins P4.0 to P4.3 are available on 44-pin PLCC/QFP package. Pins P4.5 and P4.6 are the alternative function corresponding to ALE and PSEN .
P4.0-P4.6
-3-
Publication Release Date: February 1999 Revision A2
W78LE812
BLOCK DIAGRAM
P1.0
Port 1 Port 1 Latch INT2~9 Interrupt T1 Timer 2 Timer 0 Timer 1 UART PSW ALU Stack Pointer T2 ACC
P1.7 B
Port 0 Latch Port 0
P0.0
P0.7
DPTR Temp Reg. PC
Incrementor
Addr. Reg.
P3.0
Port 3 Port 3 Latch Instruction Decoder & Sequencer SFR RAM Address
P3.7
256 bytes RAM & SFR Port 2
P2.0
Port 2 Latch
Bus & Clock Controller
P2.7
Watchdog Timer
P4.0
Port 4
Port 4 Latch
P4.6
Oscillator
Reset Block
Power control
XTAL1
XTAL2
ALE PSEN
RST
VCC
Vss
FUNCTIONAL DESCRIPTION
The W78LE812 architecture consists of a core controller surrounded by various registers, five general purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports 111 different opcodes and references both a 64K program address space and a 64K data storage space.
Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control functions for timers 0 and 1. The T2CON register provides control functions for Timer 2. RCAP2H and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a special feature of the W78LE812: it is a 16-bit up/down counter that is configured and controlled by the T2CON and T2MOD registers. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer, depending on the -4-
W78LE812
setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1. In the auto-reload mode, Timer 2 performs a up counter which is similar with standard 8052. When counting up, an overflow in Timer 2 will cause a reload from RCAP2H and RCAP2L registers. The Timer 2 also provides a programmable clock-out mode as a clock generator. To enable this mode, timer 2 has to be configured with a 16-bit auto-reload timer (C/T2 = 0, CP/RL2 = 0) and bit T2OE (T2MOD.1) must be set to 1. This mode produces a 50% duty cycle clock output and timer 2 rollovers will not generate an interrupt. The clock-out frequency depends on the oscillator frequency and the reload value of registers RCAP2H and RCAP2L. The clock-out frequency is determined by following equation: Clock-out Frequency = Oscillator Frequency / [ 4 x ( 65536 - RCAP2H, RCAP2L ) ]
OSC 1/2
TL2
TH2
1/2
T2 (P1.0)
TR2 (T2CON.2) T2EX (P1.1) EXEN2 (T2CON.3)
RCAP2L RCAP2H EXF2
Timer 2 Interrupt
T2CON.6
Timer 2 Clock-Out Mode
TIMER 2 MODE CONTROL
Bit: 7 6 5 4 3 2 1 T2OE 0 -
Mnemonic: T2MOD
Address: C9h
T2OE: Timer 2 Output Enable. This bit enables/disables the Timer 2 clock-out function.
I/O Port Options
The Port 0 and Port 3 of W78LE812 may be configured with different types by setting the bits of the Port Options Register POR that is located at 86H. The pins of Port 0 can be configured with either the open drain or standard port with internal pull-up. By the default, Port 0 is an open drain bidirectional I/O port. When the PUP bit in the POR register is set, the pins of Port 0 will perform a quasi-bi-directional I/O port with internal pull-up that is structurally the same as Port 2. The high nibble of Port 3 (P3.4 to P3.7) can be selected to serve the direct LED displays drive outputs by setting the HDx bit in the PO register. When the HDx bit is set, the corresponding pin P3.x can sink about 20mA current for driving LED display directly. After reset, the POR register is cleared and the pins of Ports 0 and 3 are the same as those of the standard 80C31. The POR register is shown below.
-5-
Publication Release Date: February 1999 Revision A2
W78LE812
Port Options Register Bit: 7 EP6 PUP EP5 EP6 6 EP5 5 4 HD7 3 HD6 2 HD5 1 HD4 0 PUP
Mnemonic: POR : Enable Port 0 weak pull-up.
Address: 86H
HD4-7 : Enable pins P3.4 to P3.7 individually with High Drive outputs. : Enable P4.5. To set this bit shifts ALE pin to the alternate function P4.5. : Enable P4.6. To set this bit shifts PSEN pin to the alternate function P4.6
Port 4
The W78LE812 has one additional bit-addressable I/O port P4 in which the port address is D8H. The Port 4 contains seven bits; P4.0 to P4.3 are only available on 44-pin PLCC/QFP package; P4.5 and P4.6 are the alternate function corresponding to pins ALE, PSEN . When program is running in the internal memory without any access to external memory, ALE and PSEN may be individually configured to the alternate functions P4.5 and P4.6 that serve as general purpose I/O pins. To enable I/O port P4.5 and P4.6, the bits EP5 and EP6 in the POR register must be set. During reset, the, ALE and PSEN perform as in the standard 80C32. The alternate functions P4.5 and P4.6 must be enabled by software. Care must be taken with the ALE pins when configured as the alternate functions. The ALE will emit pulses until either the EP5 bit in POR register or AO bit in AUXR register is set to 1. i.e. User's applications should elude the ALE pulses before software configure it with I/O port P4.5. Port 4 Bit: 7 6 P4.6 5 P4.5 4 3 P4.3 2 P4.2 1 P4.1 0 P4.0
Mnemonic: P4
Address: D8H
Interrupt System
The W78LE812 has twelve interrupt sources: INT0 and INT1; Timer 0,1 and 2; Serial Port; INT2 to INT9. Each interrupt vectors to a specific location in program memory for its interrupt service routine. Each of these sources can be individually enabled or disabled by setting or clearing the corresponding bit in Special Function Register IE0 and IE1. The individual interrupt priority level depends on the Interrupt Priority Register IP0 and IP1. Additional external interrupts INT2 to INT9 are level sensitive and may be used to awake the device from power down mode. The Port 1 interrupts can be initialized to either active HIGH or LOW via setting the Interrupt Polarity Register IX. The IRQ register contains the flags of Port 1 interrupts. Each flag in IRQ register will be set when a interrupt request is recognized but must be cleared by software. Note that the interrupt flags have to be cleared before the interrupt service routine is completed, or else another interrupt will be generated.
-6-
W78LE812
Interrupt Enable Register 0 Bit: 7 EA 6 5 ET2 4 ES 3 ET1 2 EX1 1 ET0 0 EX0
Mnemonic: IE EA : ET2: ES : ET1: EX1: ET0: EX0: Global enable. Enable/disable all interrupts. Enable Timer 2 interrupt. Enable Serial Port interrupt. Enable Timer 1 interrupt Enable external interrupt 1 Enable Timer 0 interrupt Enable external interrupt 0
Address: A8H
Interrupt Enable Register 1 Bit: 7 EX9 6 EX8 5 EX7 4 EX6 3 EX5 2 EX4 1 EX3 0 EX2
Mnemonic: IE1 EX9: EX8: EX7: EX6: EX5: EX4: EX3: EX2: Enable external interrupt 9 Enable external interrupt 8 Enable external interrupt 7 Enable external interrupt 6 Enable external interrupt 5 Enable external interrupt 4 Enable external interrupt 3 Enable external interrupt 2
Address: E8H
Note: 0 = interrupt disabled, 1 = interrupt enabled.
Interrupt Priority Register 0 Bit: 7 6 PS1 5 PT2 4 PS 3 PT1 2 PX1 1 PT0 0 PX0
Mnemonic: IP0 IP.7: PS1: PT2: PS : PT1: PX1: PT0: PX0:
Address: B8h
Unused. This bit defines the Serial port 1 interrupt priority. PS = 1 sets it to higher priority level. This bit defines the Timer 2 interrupt priority. PT2 = 1 sets it to higher priority level. This bit defines the Serial port 0 interrupt priority. PS = 1 sets it to higher priority level. This bit defines the Timer 1 interrupt priority. PT1 = 1 sets it to higher priority level. This bit defines the External interrupt 1 priority. PX1 = 1 sets it to higher priority level. This bit defines the Timer 0 interrupt priority. PT0 = 1 sets it to higher priority level. This bit defines the External interrupt 0 priority. PX0 = 1 sets it to higher priority level.
-7-
Publication Release Date: February 1999 Revision A2
W78LE812
Interrupt Priority Register 1 Bit: 7 PX9 6 PX8 5 PX7 4 PX6 3 PX5 2 PX4 1 PX3 0 PX2
Mnemonic: IP1 PX9: PX8: PX7: PX6: PX5: PX4: PX3: PX2:
Address: F8h
This bit defines the External interrupt 9 priority. PX9 = 1 sets it to higher priority level. This bit defines the External interrupt 8 priority. PX8 = 1 sets it to higher priority level. This bit defines the External interrupt 7 priority. PX7 = 1 sets it to higher priority level. This bit defines the External interrupt 6 priority. PX6 = 1 sets it to higher priority level. This bit defines the External interrupt 5 priority. PX5 = 1 sets it to higher priority level. This bit defines the External interrupt 4 priority. PX4 = 1 sets it to higher priority level. This bit defines the External interrupt 3 priority. PX3 = 1 sets it to higher priority level. This bit defines the External interrupt 2 priority. PX2 = 1 sets it to higher priority level.
Interrupt Polarity Register Bit: 7 IL9 6 IL8 5 IL7 4 IL6 3 IL5 2 IL4 1 IL3 0 IL2
Mnemonic: IX IL9: External interrupt 9 polarity level. IL8: External interrupt 8 polarity level. IL7: External interrupt 7 polarity level. IL6: External interrupt 6 polarity level. IL5: External interrupt 5 polarity level. IL4: External interrupt 4 polarity level. IL3: External interrupt 3 polarity level. IL2: External interrupt 2 polarity level. Note: 0 = active LOW, 1 = active HIGH. Interrupt Request Flag Register Bit: 7 IQ9 6 IQ8 5 IQ7 4 IQ6
Address: E9H
3 IQ5
2 IQ4
1 IQ3
0 IQ2
Mnemonic: IRQ IQ9: IQ8: IQ7: IQ6: IQ5: IQ4: IQ3: IQ2: External interrupt 9 request flag. External interrupt 8 request flag. External interrupt 7 request flag. External interrupt 6 request flag. External interrupt 5 request flag. External interrupt 4 request flag. External interrupt 3 request flag. External interrupt 2 request flag.
Address: C0H
-8-
W78LE812
Table.1 Priority level for simultaneous requests of the same priority interrupt sources SOURCE External Interrupt 0 Serial Port External Interrupt 5 Timer 0 Overflow External Interrupt 6 External Interrupt 1 External Interrupt 2 External Interrupt 7 Timer 1 Overflow Timer 2 Overflow External Interrupt 3 External Interrupt 8 External Interrupt 4 External Interrupt 9 FLAG IE0 RI + TI IQ5 TF0 IQ6 IE1 IQ2 IQ7 TF1 TF2 + EXF2 IQ3 IQ8 IQ4 IQ9 PRIORITY LEVEL (highest) VECTOR ADDRESS 0003H 0023H 0053H 000BH 005BH 0013H 003BH 0063H 001BH 002BH 0043H 006BH 004BH 0073H
(lowest)
Watchdog Timer
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the system clock. The divider output is selectable and determines the time-out interval. When the time-out occurs, a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a system monitor. This is important in real-time control applications. In case of power glitches or electro-magnetic interference, the processor may begin to execute errant code. If this is left unchecked the entire system may crash. The watchdog time-out selection will result in different time-out values depending on the clock speed. The Watchdog timer will de disabled on reset. In general, software should restart the Watchdog timer to put it into a known state. The control bits that support the Watchdog timer are discussed below. Watchdog Timer Control Register Bit: 7 ENW 6 CLRW 5 WIDL 4 3 2 PS2 1 PS1 0 PS0
Mnemonic: WDTC
Address: 8FH
ENW : Enable watch-dog if set. CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled under IDLE mode. Default is cleared.
-9-
Publication Release Date: February 1999 Revision A2
W78LE812
PS2, PS1, PS0 : Watch-dog prescaler timer select. Prescaler is selected when set PS2-0 as follows: PS2 PS1 PS0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 PRESCALER SELECT 2 4 8 16 32 64 128 256
The time-out period is obtained using the following equation :
1 x 214 x PRESCALER x 1000 x 12 mS OSC
Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6 (CLRW). After 1 is written to this bit, the 14-bit timer , prescaler and this bit will be reset on the next instruction cycle. The Watchdog timer is cleared on reset.
WIDL IDLE EXTERNAL RESET PRESCALER 14-BIT TIMER
CLEAR
ENW
OSC
1/12
INTERNAL RESET
Watchdog Timer Block Diagram
CLRW
Typical Watch-Dog time-out period when OSC = 20 MHz PS2 PS1 PS0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 WATCHDOG TIME-OUT PERIOD 19.66 mS 39.32 mS 78.64 mS 157.28 mS 314.57 mS 629.14 mS 1.25 s 2.50 s
- 10 -
W78LE812
Clock
The W78LE812 is designed to be used with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used. This makes the W78LE812 relatively insensitive to duty cycle variations in the clock. The W78LE812 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground. An external clock source should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator.
Power Management
Idle Mode The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs. Power-down Mode When the PD bit in the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks are stopped, including the oscillator. AUXR - Auxiliary Register Bit: 7 6 5 4 3 2 1 0 AO
Mnemonic: AUXR AO: Turn off ALE signal.
Address: 8Eh
Reduce EMI Emission
Because of the on-chip MTP-ROM, when a program is running in internal ROM space, the ALE will be unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it is not needed. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR, which is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off again after it has been completely accessed or the program returns to internal ROM code space..
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78LE812 is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
- 11 -
Publication Release Date: February 1999 Revision A2
W78LE812
ON-CHIP MTP ROM CHARACTERISTICS
The W78LE812 has several modes to program the on-chip MTP-ROM. All these operations are configured by the pins RST, ALE, PSEN , A9CTRL(P3.0), A13CTRL(P3.1), A14CTRL(P3.2), OECTRL(P3.3), CE (P3.6), OE (P3.7), A0(P1.0) and VPP(EA ). Moreover, the A15-A0(P2.7-P2.0, P1.7-P1.0) and the D7-D0(P0.7-P0.0) serve as the address and data bus respectively for these operations.
READ OPERATION
This operation is supported for customer to read their code and the Security bits. The data will not be valid if the Lock bit is programmed to low.
OUTPUT DISABLE CONDITION
When the
OE
is set to high, no data output appears on the D7..D0.
PROGRAM OPERATION
This operation is used to program the data to MTP ROM and the security bits. Program operation is done when the VPP is reach to VCP (12.5V) level, CE set to low, and OE set to high.
PROGRAM VERIFY OPERATION
All the programming data must be checked after program operations. This operation should be performed after each byte is programmed; it will ensure a substantial program margin.
ERASE OPERATION
An erase operation is the only way to change data from 0 to 1. This operation will erase all the MTP ROM cells and the security bits from 0 to 1. This erase operation is done when the VPP is reach to VEP level, CE set to low, and OE set to high.
ERASE VERIFY OPERATION
After an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to 1 or not. The erase verify operation automatically ensures a substantial erase margin. This operation will be done after the erase operation if VPP = VEP(14.5V), CE is high and OE is low.
PROGRAM/ERASE INHIBIT OPERATION
This operation allows parallel erasing or programming of multiple chips with different data. When P3.6( CE ) = VIH, P3.7( OE ) = VIH, erasing or programming of non-targeted chips is inhibited. So, except for the P3.6 and P3.7 pins, the individual chips may have common inputs.
- 12 -
W78LE812
COMPANY/DEVICE ID READ OPERATION
This operation is supported for MTP ROM programmer to get the company ID or device ID on the W78LE812.
OPERATIONS P3.0 (A9 P3.1 (A13 P3.2 (A14 P3.3 (OE P3.6 ( CE ) P3.7 ( OE )
EA
P2,P1 (A15..A0)
P0 (D7..D0)
NOTES
(VPP)
CTRL) CTRL) CTRL) CTRL)
Read Output Disable Program Program Verify Erase Erase Verify Program/Erase Inhibit Company ID Device ID
Notes:
0 0 0 0 1 1 X 1 1
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 1 0 1 1 0 0
0 1 1 0 1 0 1 0 0
1 1 VCP VCP VEP VEP VCP/ VEP 1 1
Address X Address Address A0:0, others: X Address X A0 = 0 A0 = 1
Data Out Hi-Z Data In Data Out Data In 0FFH Data Out X Data Out Data Out @5 @3 @4
1. All these operations happen in RST = VIH, ALE = VIL and PSEN = VIH. 2. VCP = 12.5V, VEP = 14.5V, VIH = VDD, VIL = VSS. 3. The program verify operation follows behind the program operation. 4. This erase operation will erase all the on-chip MTP-ROM cells and the Security bits. 5. The erase verify operation follows behind the erase operation.
SECURITY BITS
During the on-chip MTP-ROM operation mode, the MTP-ROM can be programmed and verified repeatedly. Until the code inside the MTP-ROM is confirmed OK, the code can be protected. The protection of MTP ROM and those operations on it are described below. The W78LE812 has several Special Setting Registers, including the Security Register and Company/Device ID Registers, which can not be accessed in normal mode. These registers can only be accessed from the MTP-ROM operation mode. Those bits of the Security Registers can not be changed once they have been programmed from high to low. They can only be reset through eraseall operation. The contents of the Company ID and Device ID registers have been set in factory. Both registers are addressed by the A0 address line during the same specific condition. The Security Register is addressed in the MTP-ROM operation mode by address #0FFFFh.
- 13 -
Publication Release Date: February 1999 Revision A2
W78LE812
D7 1 1
D6 1 1
D5 0 1
D4 1 0
D3 1 0
D2 0 0
B2
D1 1 0
B1
D0 0 0
B0
Company ID (#DAH) Device ID (#E0H) Security Bits
8KB MTP ROM Program Memory
0000h
1FFFh Reserved
Reserved
B0 : Lock bit, logic 0 : active B1 : MOVC inhibit, logic 0 : the MOVC instruction in external memory cannot access the code in internal memory. logic 1 : no restriction. B2 : Encryption logic 0 : the encryption logic enable logic 1 : the encryption logic disable Default 1 for each bit.
Security Register
0FFFFh
Special Setting Registers
Lock bit This bit is used to protect the customer's program code in the W78LE812. It may be set after the programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the MTP ROM data and Special Setting Registers can not be accessed again. MOVC Inhibit This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC instruction in external program memory from reading the internal program code. When this bit is set to logic 0, a MOVC instruction in external program memory space will be able to access code only in the external memory, not in the internal memory. A MOVC instruction in internal program memory space will always be able to access the ROM data in both internal and external memory. If this bit is logic 1, there are no restrictions on the MOVC instruction. Encryption This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will reset this bit.
+5V +5V
V DD A0 to A7 V IL V IL V IL V IL V IL V IH P1 P3.0 P3.1 P3.2 P3.3 P3.6 P3.7 X'tal1 X'tal2 Vss P0 EA/Vpp ALE RST PSEN P2 PGM DATA A0 to A7 V IL V IL V IL V IL V IH V IL P1 P3.0 P3.1 P3.2 P3.3 P3.6 P3.7 X'tal1 X'tal2 Vss
V DD P0 EA/Vpp ALE RST PSEN P2 PGM DATA V CP V IL V IH V IH A8 to A15
V CP V IL V IH V IH
A8 to A15
Programming Configuration
Programming Verification
- 14 -
W78LE812
ABSOLUTE MAXIMUM RATINGS
PARAMETER DC Power Supply Input Voltage Operating Temperature Storage Temperature SYMBOL VDD-VSS VIN TA TST MIN. -0.3 VSS -0.3 0 -55 MAX. +7.0 VDD +0.3 70 +150 UNIT V V C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
DC CHARACTERISTICS
VSS = 0V, TA = 25 C, unless otherwise specified.
SYMBOL VDD IDD
PARAMETER Operating Voltage Operating Current
SPECIFICATION MIN. 2.4 MAX. 5.5 20 3 7 1.5 50 30 +10 +10 +0 +300 0.8 0.5 0.8 0.3 UNIT V mA mA mA mA A A A A A A A V V V V
TEST CONDITIONS
VDD = 5.5V, 20 Mhz, no load, RST = 1 VDD = 2.4V, 12 Mhz, no load, RST = 1 VDD = 5.5V, 20 Mhz, no load VDD = 2.4V, 12 Mhz, no load VDD = 5.5V, no load VDD = 2.4V, no load VDD = 5.5V VIN = 0V or VDD VDD = 5.5V VSS < VIN < VDD VDD = 5.5V 0 < VIN < VDD VDD = 5.5V 0V < VIN < VDD VDD = 5.5V VIN = 2V VDD = 5.5V VDD = 2.4V VDD = 5.5V VDD = 2.4V
IIDLE IPWDN Input IIN ILK IIN2 ILK1 ITL VIL1 VIL2
Idle Current Power Down Current
-
Input Current P1, P2, P3, P4 Input Leakage Current P0, EA Input Current RST Input Leakage Current P0, EA Logic 1-to-0 Transition Current P1, P2, P3, P4 Input Low Voltage P1, P2, P3, P4 Input Low Voltage RST
[*3]
-50 -10 -10 -60 -500 0 0 0 0
- 15 -
Publication Release Date: February 1999 Revision A2
W78LE812
DC Characteristics, continued
SYMBOL VIL3 VIH1 VIH2 VIH3 Output VOL1 VOL2
PARAMETER MIN. Input Low Voltage XTAL1
[*3]
SPECIFICATION MAX. 0.8 0.6 VDD +0.2 VDD +0.2 VDD +0.2 VDD +0.2 VDD +0.2 VDD +0.2 0.45 0.25 0.45 0.25 0.22 12 5.4 18 9 24 -250 -40 -14 -3.3 V V V V V V V V V V V V mA mA mA mA mA V V V V A A mA mA UNIT 0 0 3.5 1.6 3.5 1.7 3.5 1.6 4 1.8 10 4.5 12 2.4 1.4 2.4 1.4 -120 -20 -10 -1.9
TEST CONDITIONS VDD = 5.5V VDD = 2.4V VDD = 5.5V VDD = 2.4V VDD = 5.5V VDD = 2.4V VDD = 5.5V VDD = 2.4V VDD = 4.5V, IOL = +2 mA VDD = 2.4V, IOL = +1 mA VDD = 4.5V, IOL = +4 mA VDD = 2.4V, IOL = +2 mA VDD = 4.5V, IOL = +2 mA VDD = 4.5V, VOL = 0.45V VDD = 2.4V, VOL = 0.4V VDD = 4.5V, VOL = 0.45V VDD = 2.4V, VOL = 0.4V VDD = 4.5V, VOL = 0.45V VDD = 4.5V, VOH = -100 A VDD = 2.4V, VOH = -20 A VDD = 4.5V, IOH = -400 A VDD = 2.4V, IOH = -200 A VDD = 4.5V, VOH = 2.4V VDD = 2.4V, VOH = 1.4V VDD = 4.5V, VOH = 2.4V VDD = 2.4V, VOH = 1.4V
Input High Voltage P1, P2, P3, P4, EA Input High Voltage RST Input High Voltage XTAL1
[*4]
Output Low Voltage P1, P2, P3, P4 Output Low Voltage P0, ALE, PSEN [*4]
VOL3 ISK1 ISK2
Output Low Voltage P3[*6] Sink current P1, P2, P3[5], P4<0:4> Sink current P0, ALE, PSEN , P4<5:6>
ISK3 VOH1 VOH2
Sink current P3.4 to P3.7 in High-Drive mode Output High Voltage P1, P2, P3, P4 Output High Voltage P0, ALE, PSEN
[*4]
ISR1 ISR2
Source current P1, P2, P3, P4<0:4> Source current P0, ALE, PSEN , P4<5:6>
Notes: *1. RST pin has an internal pull-down. *2. Pins of P1 and P3 can source a transition current when they are being externally driven from 1 to 0. *3. RST is a Schmitt trigger input and XTAL1 is a CMOS input. *4. P0, P2, ALE and PSEN are tested in the external access mode. *5. P3.4 to P3.7 are in normal mode. *6. P3(P3.4-P3.7) is used LED driver port by set SFR.
- 16 -
W78LE812
AC CHARACTERISTICS
The AC specifications are a function of the particular process used to manufacture the part, the ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually experience less than a 20 nS variation. The numbers below represent the performance expected from a 0.6micron CMOS process when using 2 and 4 mA output buffers.
Clock Input Waveform
XTAL1
T CH F OP, TCP TCL
PARAMETER Operating Speed Clock Period Clock High Clock Low
SYMBOL FOP TCP TCH TCL
MIN. 0 25 10 10
TYP. -
MAX. 24 -
UNIT MHz nS nS nS
NOTES 1 2 3 3
Notes: 1. The clock may be stopped indefinitely in either state. 2. The TCP specification is used as a reference in other specifications. 3. There are no duty cycle requirements on the XTAL1 input.
Program Fetch Cycle
PARAMETER Address Valid to ALE Low Address Hold from ALE Low ALE Low to PSEN Low SYMBOL TAAS TAAH TAPL TPDA TPDH TPDZ TALW TPSW MIN. 1 TCP - 1 TCP - 1 TCP - 0 0 2 TCP - 3 TCP - TYP. 2 TCP 3 TCP MAX. 2 TCP 1 TCP 1 TCP UNIT nS nS nS nS nS nS nS nS 4 4 NOTES 4 1, 4 4 2 3
PSEN Low to Data Valid Data Hold after PSEN High Data Float after PSEN High ALE Pulse Width
PSEN Pulse Width
Notes: 1. P0.0-P0.7, P2.0-P2.7 remain stable throughout entire memory cycle. 2. Memory access time is 3 TCP. 3. Data have been latched internally prior to PSEN going high. 4. "" (due to buffer driving delay and wire loading) is 20 nS.
- 17 -
Publication Release Date: February 1999 Revision A2
W78LE812
Data Read Cycle
PARAMETER ALE Low to RD Low RD Low to Data Valid Data Hold from RD High Data Float from RD High RD Pulse Width
Notes: 1. Data memory access time is 8 TCP. 2. "" (due to buffer driving delay and wire loading) is 20 nS.
SYMBOL TDAR TDDA TDDH TDDZ TDRD
MIN. 3 TCP - 0 0 6 TCP -
TYP. 6 TCP
MAX. 3 TCP + 4 TCP 2 TCP 2 TCP -
UNIT nS nS nS nS nS
NOTES 1, 2 1
2
Data Write Cycle
PARAMETER ALE Low to WR Low Data Valid to WR Low Data Hold from WR High WR Pulse Width SYMBOL TDAW TDAD TDWD TDWR MIN. 3 TCP - 1 TCP - 1 TCP - 6 TCP - TYP. 6 TCP MAX. 3 TCP + UNIT nS nS nS nS
Note: "" (due to buffer driving delay and wire loading) is 20 nS.
Port Access Cycle
PARAMETER Port Input Setup to ALE Low Port Input Hold from ALE Low Port Output to ALE SYMBOL TPDS TPDH TPDA MIN. 1 TCP 0 1 TCP TYP. MAX. UNIT nS nS nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to ALE, since it provides a convenient reference.
- 18 -
W78LE812
Program Operation
PARAMETER VPP Setup Time Data Setup Time Data Hold Time Address Setup Time Address Hold Time
CE Program Pulse Width for Program Operation OECTRL Setup Time OECTRL Hold Time OE Setup Time OE High to Output Float
SYMBOL TVPS TDS TDH TAS TAH TPWP TOCS TOCH TOES TDFP TOEV
MIN. 2.0 2.0 2.0 2.0 0 290 2.0 2.0 2.0 0 -
TYP. 300 -
MAX. 310 130 150
UNIT S S S S S S S S S nS nS
Data Valid from OE
the PSEN pin must pull in VIH status.
Note: Flash data can be accessed only in flash mode. The RST pin must pull in VIH status, the ALE pin must pull in VIL status, and
TIMING WAVEFORMS
Program Fetch Cycle
S1 XTAL1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
TALW ALE T APL PSEN T PSW TAAS PORT 2 T AAH PORT 0 Code A0-A7 Data A0-A7 Code A0-A7 Data A0-A7 T PDA T PDH, T PDZ
- 19 -
Publication Release Date: February 1999 Revision A2
W78LE812
Data Read Cycle
S4 XTAL1 ALE PSEN PORT 2
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
A8-A15 A0-A7 DATA T DAR T DDA
PORT 0 T DDH, T DDZ RD T DRD
Data Write Cycle
S4 XTAL1 ALE PSEN PORT 2 PORT 0 WR
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
A8-A15 A0-A7 DATA OUT
TDAD
T DWD
T DAW
T DWR
- 20 -
W78LE812
Port Access Cycle
S5 XTAL1
S6
S1
ALE TPDS PORT INPUT SAMPLE T PDH T PDA DATA OUT
Program Operation
Program P2, P1 VIH (A15... A0) VIL P3.6 (CE) P3.3 (OECTRL) P3.7 (OE) P0 (A7... A0) VIH VIL VIH VIL VIH VIL VIH VIL Vcp Vpp VIH TVPS Data In TDS
Program Verify
Read Verify
Address Stable TAS TPWP TAH T OCS TOCH TOES TDH DOUT TDFP
Address Valid
Data Out
TOEV
- 21 -
Publication Release Date: February 1999 Revision A2
W78LE812
TYPICAL APPLICATION CIRCUITS
Expanded External Program Memory and Crystal
V DD V DD 31 19 10 u
CRYSTAL
EA XTAL1
R 18 XTAL2 8.2 K C1 C2 12 13 14 15 1 2 3 4 5 6 7 8 INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 W78LE812 9 RST
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE TXD RXD
39 AD0 38 AD1 37 AD2 36 AD3 35 AD4 34 AD5 33 AD6 32 AD7 21 22 23 24 25 26 27 28 17 16 29 30 11 10 A8 A9 A10 A11 A12 A13 A14 A15
AD0 3 AD1 4 AD2 7 AD3 8 AD413 AD514 AD617 AD718
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 A0 5 A1 6 A2 9 A3 12 A4 15 A5 16 A6 19 A7
GND 1 OC 11 G 74373
A0 10 A1 9 A2 8 A3 7 A4 6 A5 5 A6 4 A7 3 A8 25 A9 24 A10 21 A11 23 A12 2 A13 26 A14 27 A15 1
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
O0 O1 O2 O3 O4 O5 O6 O7
11 12 13 15 16 17 18 19
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
GND 20 CE 22 OE 27512
Figure A
CRYSTAL 16 MHz 24 MHz
C1 30P 15P
C2 30P 15P
R -
Above table shows the reference values for crystal applications.
Note: C1, C2, R components refer to Figure A.
- 22 -
W78LE812
Typical Application Circuits, continued
Expanded External Data Memory and Oscillator
VDD VDD 31 19 10 u
OSCILLATOR
EA XTAL1 XTAL2 RST INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 W78LE812
18 8.2 K 9 12 13 14 15 1 2 3 4 5 6 7 8
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE TXD RXD
39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A8 A9 A10 A11 A12 A13 A14
AD0 3 AD1 4 AD2 7 AD3 8 AD4 13 AD5 14 AD6 17 AD7 18 GND 1
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
A0 A1 A2 A3 A4 A5 A6 A7
OC 11 G 74373
A0 10 A1 9 A2 8 A3 7 A4 6 A5 5 A6 4 A7 3 A8 25 A9 24 A10 21 A11 23 A12 2 A13 26 A14 1 GND 20 22 27
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 CE OE WR 20256
D0 11 D1 12 D2 13 D3 15 D4 16 D5 17 D6 18 D7 19
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
Figure B
- 23 -
Publication Release Date: February 1999 Revision A2
W78LE812
PACKAGE DIMENSIONS
40-pin DIP
Symbol
Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. Max.
0.210 0.010 0.150 0.016 0.048 0.008 0.155 0.018 0.050 0.010 2.055 0.590 0.540 0.090 0.120 0 0.630 0.650 0.600 0.545 0.100 0.130 0.160 0.022 0.054 0.014 2.070 0.610 0.550 0.110 0.140 15 0.670 0.090 14.986 13.72 2.286 3.048 0 16.00 16.51 0.254 3.81 0.406 1.219 0.203 3.937 0.457 1.27 0.254 52.20 15.24 13.84 2.54 3.302 4.064 0.559 1.372 0.356 52.58 15.494 13.97 2.794 3.556 15 17.01 2.286 5.334
D 40 21
E1
A A1 A2 B B1 c D E E1 e1 L
a
1
20 E c
eA S
Notes:
S
A A2
A1
Base Plane Seating Plane
L B B1
e1
a
eA
1. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimension D & E1 include mold mismatch and . are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec.
44-pin PLCC
HD D
6 1 44 40
Symbol
7 39
Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. Max.
0.185 0.020 0.145 0.026 0.016 0.008 0.648 0.648 0.150 0.028 0.018 0.010 0.653 0.653 0.155 0.032 0.022 0.014 0.658 0.658 0.508 3.683 0.66 0.406 0.203 16.46 16.46 3.81 0.711 0.457 0.254 16.59 16.59 3.937 0.813 0.559 0.356 16.71 16.71 4.699
E
HE
GE
17
29
18
28
c
A A1 A2 b1 b c D E e GD GE HD HE L y
Notes:
0.050 0.590 0.590 0.680 0.680 0.090
BSC 0.630 0.630 0.700 0.700 0.110 0.004
1.27 14.99 14.99 17.27 17.27 2.296
BSC 16.00 16.00 17.78 17.78 2.794 0.10
0.610 0.610 0.690 0.690 0.100
15.49 15.49 17.53 17.53 2.54
L A2 A
e
Seating Plane GD
b b1
A1 y
1. Dimension D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec.
- 24 -
W78LE812
Package Dimensions, continued
44-pin PQFP
HD D
Dimension in inch
Dimension in mm
Symbol
44 34
Min. Nom. Max.
--0.002 0.075 0.01 0.004 0.390 0.390 0.025 0.510 0.510 0.025 0.051 --0.01 0.081 0.014 0.006 0.394 0.394 0.031 0.520 0.520 0.031 0.063 --0.02 0.087 0.018 0.010 0.398 0.398 0.036 0.530 0.530 0.037 0.075 0.003 0 7
Min. Nom.
--0.05 1.90 0.25 0.101 9.9 9.9 0.635 12.95 12.95 0.65 1.295 --0.25 2.05 0.35 0.152 10.00 10.00 0.80 13.2 13.2 0.8 1.6
Max.
--0.5 2.20 0.45 0.254 10.1 10.1 0.952 13.45 13.45 0.95 1.905 0.08
1
33
E HE
11
12
e
b
22
A A1 A2 b c D E e HD HE L L1 y
Notes:
c
0
7
A2 A A1 L L1 Detail F
Seating Plane
See Detail F
y
1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeter 4. General appearance spec. should be based on final visual inspection spec.
Headquarters
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
- 25 -
Publication Release Date: February 1999 Revision A2

▲Up To Search▲

Price & Availability of W78LE812F-24

	To Download W78LE812F-24 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .